The invention relates to a method for fabricating a voltage-stable P-channel MOSFET semiconductor structure proceeding from a P-doped semiconductor substrate. The invention furthermore relates to a method for fabricating a semiconductor arrangement having at least one voltage-stable P-channel MOSFET semiconductor structure and at least one N-channel MOSFET semiconductor structure proceeding from a P-doped semiconductor substrate.
PN junctions in semiconductor components are fabricated by various known methods including diffusion, epitaxy and ion implantation. A brief overview of the diverse methods for the fabrication of bipolar transistors is given in the journal article “Advances in Bipolar VLSI” by George R. Wilson in Proceedings of the IEEE, Vol. 78, No. 11, 1990, p. 1707 to 1719.
WO 00/19503 describes a method for fabricating integrable semiconductor components proceeding from a P-doped semiconductor substrate. Firstly, a mask is applied to the semiconductor substrate for the definition of a window delimited by a peripheral edge. An N-doped well is subsequently produced in the semiconductor substrate by means of high-voltage ion implantation with an energy which is high enough that a P-doped inner zone remains at the surface of the semiconductor substrate, the edge zone of the N-doped well reaching as far as the surface of the semiconductor substrate. The further N-doped and/or P-doped zones forming the structure of the semiconductor component are then produced in the P-doped inner zone of the semiconductor substrate. The method is advantageous in so far as complex epitaxy and isolation processes may be obviated.
The known N-channel MOSFETs (NMOSFET) have two N-doped regions in a semiconductor substrate that form the source and drain of the NMOSFET. Source and drain of the NMOSFET are separated by a P-doped channel region, which is also referred to as bulk. Source and drain are thus electrically insulated from one another by two depletion layers. An electrically insulated electrode forming the gate of the MOSFET extends along the surface of the semiconductor substrate from the source to the drain.
The P-doped channel region (bulk) is generally short-circuited with the source. By applying a sufficiently high positive voltage UGS between gate and bulk or source, it is possible to induce a so-called inversion channel, which produces an N-conducting connection between drain and source, along the surface of the semiconductor substrate. If UGS is reduced to 0 V, then the inversion channel disappears, and drain and source are insulated from one another again.
Since, however, the conductivity of the inversion channel is inversely proportional to the channel length, that is to say the distance between drain and source, it is endeavoured to keep the inversion channel as short as possible (U. Tietze, Ch. Schenk, “Halbleiterschaltungstechnik” [“Semiconductor circuitry”], 11th edition, Springer, Berlin, 1999, pp. 214/215).
In the case of small channel lengths, however, the bulk doping concentration must be high enough to avoid a punch-through breakdown, that is to say a PNP breakdown between drain and source.
If the generally very highly doped drain and source regions directly adjoin the bulk doping, the corresponding (avalanche) breakdown voltages of the PN junctions are relatively low. Values of significantly less than 10 V are typical. Since the entire drain-source voltage UDS is dropped across the depletion layer between drain and bulk, the maximum permissible UDS is limited by a low drain-bulk breakdown voltage.
In discrete voltage-stable MOS transistors, this problem is avoided by arranging a weakly doped drift zone between the highly doped channel region and the very highly doped drain (U. Tietze, Ch. Schenk). This not only increases the drain-bulk breakdown voltage, but also reduces the risk of punch-through between drain and source. At the same time it is possible to realize MOSFETs with small channel lengths.
In integrated voltage-stable MOS transistors, for the sake of simplicity, a weakly doped drift zone is often implanted by means of an additional implantation, which drift zone lies within the bulk doping, however, that is to say has to overcompensate for the latter. This inevitably means that the drift zone doping is higher than the bulk doping.
In discrete power MOSFETs when a very high dielectric strength is sought, the drift zone has to be doped as weakly as possible. Therefore, a very weakly doped basic material, which constitutes the doping of the drift zone, is taken as a basis and the bulk doping is implanted or diffused therein (U. Tietze, Ch. Schenk).
Assuming that the drift zone is doped very much more weakly than the channel region, the PN junction may be regarded as abrupt, that is to say that the space charge zone that forms when a reverse voltage is present extends practically exclusively into the drift zone. In order to obtain a specific dielectric strength, both the length of the drift zone and the maximum permissible doping have to be taken into consideration. The higher the breakdown voltage is intended to be, the smaller the doping concentration in the drift zone has to be.
The maximum breakdown voltage UDG,BD in dependence on the doping concentration in the drift zone is given byUDG,BD=EBD2*∈Si*∈0/(2qN),where EBD is the breakdown field strength, ∈Si is the material-dependent permittivity, ∈0 is the permittivity of free space, q is the elementary charge and N is the doping concentration in the drift zone (S. M. Sze, “Physics of semiconductor devices”, 2nd edition, Wiley & Sons, New York, 1981, p. 100, equation).
The empirical formula for the breakdown field strength at abrupt PN junctions (S. M. Sze, “Physics of semiconductor devices”, p. 102)EBD=(4*105 V/cm2)/(1−⅓*log10(N/1016 cm−3))yields the maximum achievable drain-gate breakdown voltage in dependence on the doping concentration.
It is apparent that a lowest possible doping concentration is to be sought for the drift zone in order to achieve the highest possible dielectric strengths. In practice, involving readily reproducible components, the basic doping of the semiconductor substrate (wafer) is the lowest available doping concentration.
The integration of a voltage-stable P-channel MOSFET (PMOSFET) on a P-doped wafer presupposes an N-doped well that insulates the drain region from the substrate. Furthermore, a weakly P-doped region for the drift zone has to be produced within the N-type well. The bulk doping and the source/drain doping are subsequently introduced into this double well. There are various possibilities suitable for producing the double well.
On the basis of the known methods for fabricating semiconductor components, it is obvious, in order to obtain high dielectric strengths, to provide a weakly P-doped epitaxial layer on a highly doped N-type layer (buried layer). However, this method is technically demanding and cost-intensive on account of the epitaxy step and the lateral isolation required. Furthermore, the method is lengthy on account of the long diffusion processes. A further disadvantage resides in the poor utilization of area, leading to large components.
If less stringent requirements are made of the dielectric strength, it is possible to resort to the known diffusion processes for producing a P-doped region in an N-doped well. In this case, however, a multiple overcompensation of N-type and P-type dopings arises at the surface in the drift region, as a result of which the minimum doping level of the drift zone is limited for reasons of reproducibility. Consequently, this method is not appropriate for voltage-stable MOSFET transistors.